A crystalline silicon photovoltaic (PV) cell typically has a first surface operable to receive light and a second surface opposite the first surface. The first surface is doped to form the emitter of the PV cell and has a plurality of electrical contacts formed therein. The second surface has at least one electrical contact.
The first contacts are typically formed as a plurality of parallel spaced apart “fingers” that extend across the entire first surface. The fingers are formed by screen printing a metallic paste onto the first surface in a desired pattern. The metallic paste is fired by high temperature treatment to form a conductive metal pattern that also forms electrical contact to the emitter. Additional paste may be provided to create bus bars that extend at right angles to the fingers, to collect electric current from the fingers. The bus bars may be wider than the fingers to enable them to carry the current collected from the fingers.
Screen printing and firing technology imposes limitations on solar cell efficiency improvements due to a restriction on emitter thickness. When the emitter thickness is not sufficient, diffusion of the contact metal during firing may exceed the emitter depth leading to electrical shunting through the pn junction. Furthermore, a thin emitter usually implies a lower level of doping which can lead to poor electrical contact between the emitter and the metal contact. Some screen printing technology requires an emitter thickness of greater than 0.2 micrometers, corresponding to a sheet resistance below 65 ohm/sq. However, an emitter with a sheet resistance of greater than about 100 ohm/sq and thickness of less than about 0.2 micrometers provides a substantial gain in cell efficiency mainly due to lower optical losses in the blue spectral region. An emitter with these properties is referred to as a shallow emitter. In order to increase the conversion efficiency of solar cells that employ the abovementioned screen printed metallization, emitter design parameters may be optimized such that under a screen printed finger, an emitter thickness is sufficiently, high while in light-illuminated areas, the emitter thickness is substantially thinner. An emitter with these differing thicknesses is referred to as a selective emitter. In a selective emitter, sufficient emitter thickness and high dopant concentration in areas under current collecting fingers and bus bars ensures low resistance electrical contacts between the semiconductor substrate and the fingers and bus bars without shunting the p/n junction. Although the use of a selective emitter has proved to be effective in improving PV cell efficiency, implementation of a selective emitter in practice, is quite complicated.
The emitter in PV cells may be produced by a dopant diffusion process. In such a process, the wafer is heated in the presence of a desired dopant or its precursor, allowing a controlled quantity of the dopant to diffuse a certain depth into the wafer (referred to as the dopant diffusion or the emitter diffusion).
Selective emitters have been attempted by a number of strategies. An etchback process as described in U.S. Pat. No. 8,293,568 involves producing a uniform deep emitter across the substrate, and etching back selected areas to make those areas shallow. In contrast, there are methods that start with a shallow emitter and produce regions that are deeper either by the use of laser treatment additional chemical treatments, as described in US 2011/0214727. A very promising route to the selective emitter cell involves the application of patterned barrier layers prior to doping, such that doping will be high where there is little or no barrier, and doping will be lower where there is a more substantial barrier.
One barrier approach uses silicon dioxide deposited by thermal oxidation at elevated temperature (800 to 1100 C) followed by patterning of the oxide using laser ablation or etching as described in U.S. Patent Appl. Pub. 2011/0214727. However, this process requires that the substrate be subjected to an expensive high temperature oxidation. This additional high temperature heating may cause defects that may be detrimental to charge carrier lifetime and cell performance. One method to apply silicon nitride as the barrier involves treatment of the wafer in a nitrogen plasma as described in U.S. Pat. No. 8,288,193. However, this process requires a vacuum plasma treatment of the substrate. Another method to form silicon oxide as the barrier involves electrochemical formation as described in U.S. Pat. No. 8,293,568. However, electrochemical treatments involve a high degree of equipment complexity to permit electrical contact to substrates.
We have found that the liquid phase deposition (LPD) of silicon dioxide forms an excellent barrier to diffusion of phosphorous at high temperature. The LPD process is advantageous because it can be performed at low temperature in a liquid bath without the need for any addition physical forces (such as electric current). We have further found that the LPD films provide excellent function as barrier layers to dopant diffusion when they are patterned by prior application of certain polymer resists.